PIC18F83J11T-I/PT【PDF 47/332 页】IC PIC MCU FLASH 4KX16 80TQFP

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PIC18F85J11 FAMILY

DS39774D-page 140

2010 Microchip Technology Inc.

11.6

PORTE, TRISE and

LATE Registers

PORTE is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction and Output Latch registers are

TRISE and LATE. All pins on PORTE are digital only

and tolerate voltages up to 5.5V.

All pins on PORTE are implemented with Schmitt Trig-

ger input buffers. Each pin is individually configurable

as an input or output. The RE7 pin is also configurable

for open-drain output when CCP2 is active on this pin.

Open-drain configuration is selected by setting the

CCP2OD control bit (TRISG<6>)

Each of the PORTE pins has a weak internal pull-up. A

single control bit can turn off all the pull-ups. This is

performed by clearing bit, REPU (PORTG<6>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on any device Reset.

On 80-pin devices, PORTE is multiplexed with the

system bus as part of the external memory interface.

I/O port and other functions are only available when the

interface is disabled by setting the EBDIS bit

(MEMCON<7>). When the interface is enabled,

PORTE is the high-order byte of the multiplexed

address/data bus (AD<15:8>). The TRISE bits are also

overridden.

When the Parallel Slave Port is active on PORTD, three

of the PORTE pins (RE0, RE1 and RE2) are configured

as digital control inputs for the port. The control

functions are summarized in Table 11-11. The reconfig-

uration occurs automatically when the PSPMODE

control bit (PSPCON<4>) is set. Users must still make

certain the corresponding TRISE bits are set to

configure these pins as digital inputs.

RE7 can also be configured as the alternate peripheral

pin for the CCP2 module. This is done by clearing the

CCP2MX Configuration bit.

EXAMPLE 11-5:

INITIALIZING PORTE

Note:

These pins are configured as digital inputs

on any device Reset.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

03h

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE<1:0> as inputs

; RE<7:2> as outputs

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